The relentless drive to higher performance, more functions and lower cost for IC products requires new and improved process technologies. The ability to develop these technologies with optimal PPAC (power-performance-area-cost) and TTM (time-to-market) is a key competitive advantage for IC foundries and IDMs.
Our comprehensive test chip strategy covers the full spectrum of development deliverables, including both the core technology and critical enablement requirements (rules, models, design-process interactions and etc.). With our streamlined test chip design, test and analysis infra-structure and services, our customers have reaped the benefits of shorter learning cycle, more actionable insights that pull in development schedule and improved development quality metrics.
? PCell based design approach plus custom-design support provide a systematic approach to address process complexity
? Addressable test chip technology optimizes area utilization in the limited tape-out area
? Fast parametric testers accelerate data collection
? Analysis software reveals inherent insights from vast amount of process and test chip data